Ty Garibay Joins ArterisIP as Chief Technology Officer

CAMPBELL, Calif. (PRWEB)

ArterisIP, the innovative supplier of silicon-proven commercial system-on-chip (SoC) interconnect IP, today announced the appointment of Ty Garibay as ArterisIP’s Chief Technology Officer (CTO). Mr. Garibay will play a key role in extending ArterisIP’s innovation leadership in the on-chip interconnect semiconductor IP market, molding the company’s technical vision and driving corporate technology strategy as the industry adapts to serve the need for functionally safe machine learning and autonomous driving systems.

“Ty is a highly respected technologist with a strong reputation and an excellent depth of knowledge in on-chip communications, SoC architecture and IC design. He is a well-known industry thought leader with a proven track record of semiconductor innovation, deep customer relationships and breakthrough product definition,” said K. Charles Janac, President and CEO of Arteris. “We are delighted to have Ty join us as we drive to continue our undisputed leadership in on-chip communications and interconnect IP.”

Mr. Garibay has played key roles in the development of microprocessor and system-on-chip architectures and technologies, serving in architect and design leadership roles at Motorola, Cyrix, SGI, and Alchemy Semiconductor. He managed ARM’s Austin Design Center and also ARM cores development and IC engineering for Texas Instruments’ OMAP application processors group. Most recently, Mr. Garibay was Vice President of IC Engineering for Altera, and later led FPGA IC design at Intel after it acquired Altera in late 2015. Mr. Garibay has authored and co-authored 34 patents, and has been published in multiple technical journals and conferences.

“As a long-time ArterisIP customer and partner, I am excited to have the opportunity to contribute directly to the company’s success,” said Ty Garibay, CTO of ArterisIP. “The ArterisIP team has established themselves as not only the leading provider of commercial network-on-chip based interconnect IP, but also as a trusted technology partner to most of the world’s leading SoC design teams. I look forward to carrying on this tradition of excellence as part of this highly skilled team.”

A high-resolution photograph of Garibay can be found here at the ArterisIP website.

About ArterisIP

Headquartered in Silicon Valley, ArterisIP provides system-on-chip (SoC) interconnect IP to accelerate SoC semiconductor assembly for a wide range of applications from automobiles to mobile phones, cameras, IoT, SSD controllers and servers for customers such as Samsung, Huawei / HiSilicon, Mobileye, Altera (Intel), and Texas Instruments. ArterisIP products include the Ncore cache coherent and FlexNoC non-coherent interconnect IP, as well as optional Resilience Package (functional safety) and PIANO automated timing closure capabilities. Customer results obtained by using the ArterisIP product line include lower power, higher performance, more efficient design reuse and faster SoC development, leading to lower development and production costs. For more information, visit http://www.arteris.com or find us on LinkedIn at https://www.linkedin.com/company/arteris.

Arteris, ArterisIP, FlexNoC. Ncore, PIANO, and the ArterisIP logo are trademarks of Arteris, Inc. All other product or service names are the property of their respective owners.

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